A liquid crystal display panel displays an image by adopting a matrix of M*N pixels which are scanned row by row. Drivers for Thin Film Transistor-Liquid Crystal Display (TFT-LCD) mainly comprise a gate driver and a data driver, wherein the gate driver supplies gate lines of the liquid crystal display panel with signals converted by a shift register from input clock signals.
A shift register is commonly adopted in a gate driver of a liquid crystal display panel, and each of gate lines is connected to a stage of circuit units in the shift register. Gate input signals are outputted from the gate driving circuit, so as to scan pixels row by row. The Gate Driving Circuit can be set in a display panel by adopting a packaging manner of Chip on Array (COF) or Chip on Glass (COG) technology. In a display panel, it is also possible to form integrated circuit units on the display panel by TFTs. For a liquid crystal display panel, Gate on Array (GOA) technology can reduce the cost of product, and can improve productivity by removing one process.
A typical structure of an existing shift register unit is as shown in FIG. 1. FIG. 2 is an operational timing sequence diagram of the shift register unit as shown in FIG. 1, and the operation principle of the shift register unit is as follows.
During a first phase, a signal input terminal Input is at a high level, the signal received at the signal input terminal is an output signal of a previous stage of shift register unit, such that a transistor M1′ is turned on; when a first clock signal input terminal CLK1 is at a low level, a capacitor C1′ is charged by the high level signal at the input terminal, such that a potential at a first node (PU node) is pulled up and transistors M5′ and M6′ are turned on; when the ratio of the size of transistor M5′ to that of transistor M6′ is designed such that the potential at a PD node is at low at this time, transistors M8′ and M9′ are turned off, and thus the stability of the output signal can be ensured.
During a second phase, the signal input terminal Input is at a low level, transistor M1′ is turned off, the first node PU continuously remains at the high potential, and transistor M3′ remains in an ON state. At this time, the first clock signal input terminal CLK1 is at a high potential, the voltage at the first node is raised up due to bootstrapping effect and a driving signal is finally outputted to the output terminal; at this time, the first node (PU node) is at a high potential, transistor M6′ still in an ON state, such that transistors M8′ and M9′ are continuously in an OFF state, and thus the stability of the output signal can be ensured.
During a third phase, a reset signal input terminal is connected to an output terminal of a shift register at a next stage, and an output signal G(n+1) of the next stage (i.e. signal at a reset terminal Reset) is at a high level. Transistors M2′ and M4′ are turned on by the high level signal at the reset signal input terminal, such that the first node (PU node) and the output terminal Output are pulled down and transistor M3′ is turned off, and the output signal is pulled down to the potential VGL.
During a fourth phase, a second clock signal input terminal CLK2 is at a low level, the second clock signal and the first clock signal have a same period but have opposite phases. The first clock signal input terminal CLK1 is at a high potential, transistor M5′ is turned off, the potential at the second node (PD node) is at low potential, transistors M8′ and M9′ are turned off. At this time, the first node (PU node) and the output terminal Output are discharged through transistors M2′ and M4′ respectively at the previous phase, transistor M6′ is in an OFF state, such that the second node (PD node) is not discharged.
During a fifth phase, the second clock signal input terminal CLK2 is at a high potential, the transistor M5′ is turned on since the second clock signal input terminal CLK2 is at the high potential, and the potential at the second node (PD node) is pulled up, such that the transistors M8′ and M9′ are turned on, noises at the first node (PU node) and the output terminal Output are removed, such that the coupling noise voltage caused by the first clock signal input terminal CLK1 is eliminated, the low level of the output signal is ensured and the stability of the output signal can be ensured.
However, the above-described shift register unit can only remove noise at the output terminal during partial time of the operational period, but is in a floating state during other time periods, which renders large noise in the output signal at the output terminal of the shift register unit, thus causing an error output signal and potential safety problems.